From ec269956554cbed8e283e9b6ef21d3b02f054db9 Mon Sep 17 00:00:00 2001
From: Kaushal Modi <kaushal.modi@gmail.com>
Date: Mon, 26 Sep 2016 15:24:35 -0400
Subject: [PATCH] Add SystemVerilog (SV) type

---
 src/types.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/types.rs b/src/types.rs
index 4de6573b..2b60bcbe 100644
--- a/src/types.rs
+++ b/src/types.rs
@@ -70,6 +70,7 @@ const TYPE_EXTENSIONS: &'static [(&'static str, &'static [&'static str])] = &[
     ("scala", &["*.scala"]),
     ("sh", &["*.bash", "*.csh", "*.ksh", "*.sh", "*.tcsh"]),
     ("sql", &["*.sql"]),
+    ("sv", &["*.v", "*.vg", "*.sv", "*.svh", "*.h"]),
     ("swift", &["*.swift"]),
     ("tex", &["*.tex", "*.cls", "*.sty"]),
     ("ts", &["*.ts", "*.tsx"]),